OpenFreebox

InterfaceSerieHD

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* L'Interface Serie du boitier HD


Tout est dit dans le PlanHD, tout comme pour la V4, un chip de type MAX3232 reste necessaire.

Voila se que l'on peut trouver en sortie de l'interface serie lors du boot du boitier HD:

xosPc0 serial#xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx subid 0xc4
xenv cs2 ok
Power supply: OK
DRAM0 OK (b)
DRAM1 OK (b)
zboot ok
Revb/ES7 processor, using cl 0x11 for test
>
* * * * * * * * * * * * * * * * * * * * * * *
* SMP863x zboot start ...
* Version: ZBOOT-2.0.0-FBX_1.3
* Started at 0x93000000.
* Configurations (chip revision: 4):
* Use 8KB DRAM as stack.
* Support XLoad format.
* Enabled memory test mode.
* * * * * * * * * * * * * * * * * * * * * * *
Boot from flash (0x48000000) mapped to 0xac000000.
Found XENV block at 0xac0000
CPU clock frequency: 252.00MHz.
System clock frequency: 168.00MHz.
DRAM0 dunit_cfg/delay0_ctrl (0xe63111ba/0x00097787).
DRAM1 dunit_cfg/delay0_ctrl (0xe34111ba/0x00097686).
Using UART port 0 as console.
XENV version: "1.3"
Board ID.: "FBX5B"
Chip Revision: 0x8635:0x83 .. Mismatched.
Setting up H/W from XENV block at 0xac000000.
Setting <SYSCLK avclk_mux> to 0x00000000.
Setting <SYSCLK hostclk_mux> to 0x00000100.
Setting <IRQ rise edge trigger lo> to 0xff28ca00.
Setting <IRQ fall edge trigger lo> to 0x0000
Setting <IRQ rise edge trigger hi> to 0x000000ff.
Setting <IRQ fall edge trigger hi> to 0x00000000.
Setting <IRQ GPIO map> to 0x0d090800.
Setting <PB default timing> to 0x01090008.
Setting <PB timing0> to 0x01090008.
Setting <PB Use timing0> to 0x000003fc.
Setting <PB timing1> to 0x00110101.
Setting <PB Use timing1> to 0x000003f3.
PB cs config: 0x000c10c0 (use 0x000c10c0)
Enabled Devices: 0x00003efe
BM/IDE PCIHost Ethernet IR FIP I2CM I2CS USB PCIDev1 PCIDev2 PCIDev3 PCIDev4

PCI IRQ rou
IDSEL 1: INTA(#14) INTB(#14) INTC(#14) INTD(#14)
IDSEL 2: INTA(#14) INTB(#14) INTC(#14) INTD(#14)
IDSEL 3: INTA(#15) INTB(#15) INTC(#15) INTD(#15)
IDSEL 4: INTA(#15) INTB(#15) INTC(#15) INTD(#15)
Setting up Clean Divider 2 to 96000000Hz.
Setting up Clean Divider 4 to 33000000Hz.
Setting up Clean Divider 5 to 25000000Hz.
Setting up Clean Divider 6 to 25000000Hz.
Setting up Clean Divider 7 to 20480000Hz.
GPIO dir/data = 0x07fec040/0x03bac040
UART0 GPIO mode/dir/data = 0x6e/0x60/0x40
UART1 GPIO mode/dir/data = 0x00/0x00/0x00
XENV block processing completed.
Found existing memcfg: DRAM0(0x04000000), DRAM1(0x04000000)

# # # # # # # # # # # # # # # # # # # #
# Starting fbx boot process...
# # # # # # # # # # # # # # # # # # # #

# # # Standard boot

-> FIP keys = 0x00000000
-> Processing partition BANK1 (7)