Setting <SYSCLK avclk_mux> to 0x00000000.
Setting <SYSCLK hostclk_mux> to 0x00000100.
Setting <IRQ rise edge trigger lo> to 0xff28ca00.
Setting <IRQ fall edge trigger lo> to 0x0000
Setting <IRQ rise edge trigger hi> to 0x000000ff.
Setting <IRQ fall edge trigger hi> to 0x00000000.
Setting <IRQ GPIO map> to 0x0d090800.
Setting <PB default timing> to 0x01090008.
Setting <PB timing0> to 0x01090008.
Setting <PB Use timing0> to 0x000003fc.
Setting <PB timing1> to 0x00110101.
Setting <PB Use timing1> to 0x000003f3.
PB cs config: 0x000c10c0 (use 0x000c10c0)
Enabled Devices: 0x00003efe
BM/IDE PCIHost Ethernet IR FIP I2CM I2CS USB PCIDev1 PCIDev2 PCIDev3 PCIDev4
PCI IRQ rou
IDSEL 1: INTA(#14) INTB(#14) INTC(#14) INTD(#14)
IDSEL 2: INTA(#14) INTB(#14) INTC(#14) INTD(#14)
IDSEL 3: INTA(#15) INTB(#15) INTC(#15) INTD(#15)
IDSEL 4: INTA(#15) INTB(#15) INTC(#15) INTD(#15)
Setting up Clean Divider 2 to 96000000Hz.
Setting up Clean Divider 4 to 33000000Hz.
Setting up Clean Divider 5 to 25000000Hz.
Setting up Clean Divider 6 to 25000000Hz.
Setting up Clean Divider 7 to 20480000Hz.
GPIO dir/data = 0x07fec040/0x03bac040
UART0 GPIO mode/dir/data = 0x6e/0x60/0x40
UART1 GPIO mode/dir/data = 0x00/0x00/0x00
XENV block processing completed.